Dimmer having a power supply monitoring circuit

ABSTRACT

A two-wire dimmer for control of a lighting load from an alternating-current (AC) power source includes a semiconductor switch, a power supply, and a control circuit. The power supply includes an energy storage input capacitor that is able to charge only when the semiconductor switch is non-conductive. The control circuit continuously monitors the voltage on the input capacitor and automatically decreases the maximum allowable conduction time of the semiconductor switch when the voltage falls to a level that will not guarantee proper operation of the power supply. The dimmer of the present invention is able to provide the maximum possible conduction time of the semiconductor switch at high end (i.e., maximum light intensity) while simultaneously ensuring sufficient charging time for proper operation of the power supply, and hence, the dimmer.

FIELD OF THE INVENTION

The present invention relates to a two-wire load control device,specifically a two-wire dimmer for electronic low-voltage (ELV) lightingloads.

BACKGROUND OF THE INVENTION

Low-voltage lighting, such as electronic low-voltage (ELV) and magneticlow-voltage (MLV) lighting, is becoming very popular. Low-voltage lampsallow for excellent, precise sources of illumination, extended lamplife, higher efficiencies than incandescent lamps, and unique lightingfixtures, such as track lighting. To power an electronic low-voltagelamp, an ELV transformer is required to reduce a line voltage (typically120 V_(AC) or 240 V_(AC)) to a low-voltage level (such as 12 volts or 24volts) to power the ELV lamp.

Many prior art two-wire dimmers exist for control of ELV lighting loads.A conventional two-wire dimmer has two connections: a “hot” connectionto an alternating-current (AC) power supply and a “dimmed hot”connection to the lighting load. Standard dimmers use one or moresemiconductor switches, such as triacs or field effect transistors(FETs), to control the current delivered to the lighting load and thuscontrol the intensity of the light. The semiconductor switches aretypically coupled between the hot and dimmed hot connections of thedimmer.

Since an ELV transformer is normally characterized by a largecapacitance across the primary winding, the ELV lighting load istypically dimmed using reverse phase-control dimming (often called“trailing-edge” dimming), in which the dimmer includes two FETs inanti-serial connection. One FET conducts during the first, positivehalf-cycle of the AC waveform and the other FET conducts during thesecond, negative half-cycle of the AC waveform. The FETs are alternatelyturned on at the beginning of each half-cycle of the AC power supply andthen turned off at some time during the half-cycle depending upon thedesired intensity of the lamp. To execute reverse phase-control dimming,many ELV dimmers include a microprocessor to control the switching ofthe FETs.

In order to provide a direct-current (DC) voltage to power themicroprocessor and other low-voltage circuitry, the dimmer includes apower supply, such as a cat-ear power supply. A cat-ear power supplydraws current only near the zero-crossings of the AC waveforms andderives its name from the shape of the waveform of the current that itdraws from the AC supply. The power supply must draw current through theconnected ELV lighting load. The FETs must both be turned off(non-conducting) at the times when the power supply is charging. So, theFETs cannot be turned on for the entire length of a half-cycle, evenwhen the maximum voltage across the load is desired.

To ensure that the power supply is able to draw enough current tomaintain its output voltage at all times, the FETs are turned off at theend of each half-cycle for at least a minimum off-time. The properoperation of the ELV dimmer is constrained by a number of worst-caseoperating conditions, such as high current draw by the low-voltagecircuitry, worst-case line voltage input (i.e. when the AC power supplyvoltage is lower than normal), and worst-case load conditions (such asthe number and the wattage of the lamps, the types of ELV transformers,and variations in the operating characteristics of the ELVtransformers). By considering these worst-case conditions, the minimumoff-time is determined by calculating the off-time that will guaranteethat the power supply will charge fully for even the worst-caseconditions. The resulting off-time generally ends up being a largeportion of each half-cycle and constrains the maximum light level of theattached load.

However, the worst-case condition is not normally encountered inpractice, and under typical conditions, the FETs could normally beturned off for a shorter amount of time at the end of each half-cycle,thus conducting current to the load for a greater amount of timeresulting in a higher intensity of the load that is closer to theintensity achieved when only a standard wall switch is connected inseries with the load. Prior art dimmers have held the minimum off-timeconstant under all conditions, and thus, have suffered from a smalldimming range.

Thus, there exists a need for an ELV dimmer that includes a power supplyand has an increased dimming range. More specifically, there exists aneed for an ELV dimmer that includes a power supply and is able to drivean ELV lighting load above the maximum dimming level of prior art ELVdimmers without compromising the operation of the power supply.

SUMMARY OF THE INVENTION

According to the present invention, a two-wire dimmer for control of alighting load from a source of AC voltage includes a semiconductorswitch, a power supply, and a control circuit. The semiconductor switchis operable to be coupled between the source of AC voltage and thelighting load and has a conducting state and a non-conducting state. Thepower supply has an input that receives an input voltage and is operableto draw current from the source of AC voltage during the non-conductingstate of the semiconductor switch. The control circuit is operable tocontrol the semiconductor switch into the conducting state for anon-time each half-cycle of the AC voltage and is coupled to the input ofthe power supply for monitoring the input voltage of the power supply.The control circuit is operable to decrease the on-time when the inputvoltage of the power supply falls below a first predetermined level.Further, the control circuit is operable to increase the on-time whenthe input voltage rises above a second predetermined level greater thanthe first level.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a simplified block diagram of the two-wire dimmer of thepresent invention;

FIG. 2a is a waveform of the dimmed hot voltage of the dimmer of FIG. 1;

FIG. 2b is a waveform of the voltage across the dimmer of FIG. 1;

FIG. 3 is a flowchart of the process implemented by a control circuit ofthe dimmer of FIG. 1;

FIG. 4 shows voltage waveforms of the dimmer of FIG. 1 during a firstpart of the process of FIG. 3; and

FIG. 5 shows voltage waveforms of the dimmer of FIG. 1 during a secondpart of the process of FIG. 3.

DETAILED DESCRIPTION OF THE INVENTION

The foregoing summary, as well as the following detailed description ofthe preferred embodiments, is better understood when read in conjunctionwith the appended drawings. For the purposes of illustrating theinvention, there is shown in the drawings an embodiment that ispresently preferred, in which like numerals represent similar partsthroughout the several views of the drawings, it being understood,however, that the invention is not limited to the specific methods andinstrumentalities disclosed.

FIG. 1 shows the two-wire dimmer 100 of the present invention, which isconnected in series between an AC power supply 102 and an ELV lightingload 104. The dimmer 100 has two connections: a HOT connection 106 tothe AC power supply 102 and a DIMMED HOT connection 108 to the lightingload 104. Since ELV loads operate at a low-voltage level (such as 12volts or 24 volts), a step-down transformer XFMR is required for the ELVlamp 104A. The ELV transformer XFMR is typically characterized by alarge capacitance C_(ELV) across the primary winding.

To control the AC voltage delivered to the ELV load 104, twofield-effect transistors (FETs) 110, 112 are provided in anti-serialconnection between the HOT terminal 106 and the DIMMED HOT terminal 108.The first FET 110 conducts during the positive half-cycle of the ACwaveform and the second FET 112 conducts during the negative half-cycleof the AC waveform. ELV lighting loads are dimmed using reverse-phasecontrol dimming, in which the FETs are alternately turned on at thebeginning of each half-cycle of the AC power supply and then turned offat some time during the half-cycle depending upon the desired intensityof the lamp. The conduction state of the FETs 110, 112 is determined bya control circuit 114 that interfaces to the FETs through a gate drivecircuit 116. To execute reverse-phase control dimming, the controlcircuit 114 includes a microprocessor to control the switching of theFETs 110, 112.

The ELV dimmer also includes a plurality of buttons 118 for input from auser, and a plurality of light emitting diodes (LEDs) 120 for feedbackto the user. The control circuit 114 determines the appropriate dimminglevel of the ELV lamp 104A from the input from the buttons 118.

A zero-cross circuit 122 provides a control signal to the controlcircuit 114 that identifies the zero-crossings of the AC supply voltage.A zero-crossing is defined as the time at which the AC supply voltageequals zero at the beginning of each half-cycle. The zero-cross circuit122 receives the AC supply voltage through diode D1 in the positivehalf-cycle and through diode D2 in the negative half-cycle. The controlcircuit 114 determines when to turn off the FETs each half-cycle bytiming from each zero-crossing of the AC supply voltage.

In order to provide a DC voltage (V_(CC)) to power the microprocessor ofthe control circuit 114 and the other low-voltage circuitry, the dimmer100 includes a power supply 124. The power supply 124 is only able tocharge when the FETs 110, 112 are both turned off (non-conducting) andthere is a voltage potential across the dimmer. Since there are only twoconnections on a two-wire dimmer, the power supply must draw a leakagecurrent through the connected ELV lighting load 104. For example, duringthe positive half-cycle, current flows from the AC supply 102 throughdiode D1 to the power supply 124 and then, via circuit common, outthrough the body diode of the second FET 112 and through the load 104back to the AC supply. The power supply 124 may be implemented as a“cat-ear” power supply, which only draws current near the zero-crossingsof the AC waveform, or as a standard switch-mode power supply.

In a typical two-wire dimmer, the power supply 124 is implemented as a“cat-ear” power supply, which only draws current near the zero-crossingsof the AC waveforms. The power supply 124 has an input capacitor C1 andan output capacitor C2. The output capacitor C2 holds the output of thepower supply Vcc at a constant DC voltage to provide power for thecontrol circuit 114. The input of the power supply 124 is coupled to theHot and Dimmed Hot terminals through the two diodes D1, D2, such thatthe input capacitor C1 charges during both the positive and negativehalf-cycles.

The dimmer 100 also includes a voltage divider that comprises tworesistors R1, R2 and is coupled between the input of the power supply124 and circuit common. The voltage divider produces a sense voltageV_(S) at the junction of the two resistors. The sense voltage V_(S) isprovided to the control circuit 114 such that the control circuit isable to monitor the voltage level at the input of the power supply 124.The microprocessor in the control circuit 114 preferably includes ananalog-to-digital converter (ADC) for sampling the value of the sensevoltage V_(S). The resistors R1, R2 are preferably sized to ensure thatthe maximum voltage at the pin of the microprocessor of the controlcircuit 114 does not exceed the power supply output V_(CC). For example,if the input voltage to the waveform is 240 V_(RMS) and the power supplyoutput V_(CC) is 3.3 V_(DC), then the values of R1 and R2 can be sizedto 450 kΩ and 3 kΩ, respectively, in order to ensure that the magnitudeof the sense voltage is less than 3.3 V_(DC). Alternatively, the voltagedivider could be coupled between the output voltage (or anotheroperating voltage) of the power supply 124 and circuit common to providea signal to the control circuit 114 that is representative of thepresent operating conditions of the power supply.

According to the present invention, the control circuit 114 monitors thesense voltage V_(S) and decreases the conduction times of the FETs 110,112 when the sense voltage V_(S) drops below a first predeterminedvoltage threshold V₁. Further, the control circuit 114 increases theconduction times of the FETs 110, 112 when the sense voltage then risesabove a second predetermined voltage threshold V₂, greater than thefirst threshold. In a preferred embodiment of the present invention(when used with an input voltage of 240 V_(RMS)), the first and secondvoltage thresholds V₁ and V₂ are set to 0.67 V_(DC) and 0.8 V_(DC),respectively, which correspond to voltages of 100 V_(DC) and 120 V_(DC)at the input of the power supply 124. Alternatively, if themicroprocessor does not include an ADC, the dimmer 100 could include ahardware comparison circuit, including one or more comparator integratedcircuits, to compare the sense voltage with the first and second voltagethresholds and then provide a logic signal to the microprocessor.

FIG. 2a shows examples of a dimmed hot voltage 210 measured from theDimmed Hot terminal 108 of the dimmer 100 to neutral (i.e. the voltageacross the lighting load 104). The dashed line represents the AC voltage220 measured across the AC power supply 102. The period of the ACvoltage 220 is split into two equal half-cycles having periods T_(H).The dimmed hot voltage 210 has a value equal to the AC voltage 220during the time t_(ON) when one of the FETs is conducting. Conversely,the dimmed hot voltage 210 has a value equal to zero during the timet_(OFF) when neither FET is conducting. The control circuit 114 is ableto control the intensity of the load by controlling the on-time t_(ON).The longer the FETs conduct during each half-cycle, the greater theintensity of the lighting load 104 will be.

FIG. 2b shows an example of the dimmer voltage 230 measured from the Hotterminal 106 to the Dimmed Hot terminal 108 of the dimmer (i.e. thevoltage across the dimmer) The power supply 124 is only able to chargeduring the off-time t_(OFF) because the off-time is the only time duringeach half-cycle when there is a voltage potential across the FETs andthus across the power supply 124. Conversely, when the FETs areconducting during the on-time t_(ON), the FETs form a low impedance paththrough the dimmer 100 and the input capacitor C1 of the power supply124 is unable to charge.

With prior art ELV dimmers, a maximum off-timet_(OFF-MAX-WC) needed tocharge the power supply during worst-case conditions was used todetermine the maximum on-time t_(ON-MAX-WC) of the dimmer. Theworst-case conditions may include a low-line AC input voltage or a highcurrent drawn from the power supply by the microprocessor and otherlow-voltage components. However, the dimmer is not always operating withthe worst-case conditions and it may be possible to increase the on-timeabove the maximum on-time t_(ON-MAX-WC) in order to provide a greaterlight output of the lighting load 104 at high-end.

The dimmer 100 of the present invention has a maximum on-time limit,t_(ON-MAX-LIMIT) that is greater than the worst-case on-timet_(ON-MAX-WC). The maximum on-time limit t_(ON-MAX-LIMIT) of the dimmer100 is determined from the appropriate off-time required to charge theinput capacitor C1 of the power supply 124 during normal operatingconditions. The dimmer 100 also has a dynamic maximum on-time,t_(ON-MAX), that the control circuit 114 is operable to control from onehalf-cycle to the next. The dynamic maximum on-time t_(ON-MAX) cannotexceed the maximum on-time limit t_(ON-MAX-LIMIT), but can be decreasedbelow the limit in order to increase the off-time of the FETs to allowthe input capacitor C1 of the power supply 124 more time to charge. Bydriving the on-time of the FETs above the worst-case on-timet_(ON-MAX-WC), the dimmer 100 of the present invention is able toachieve a greater light output of the connected lighting load 104 thanprior art ELV dimmers. However, when the on-time of the FETs is greaterthan the worst-case on-time t_(ON-MAX-WC), there is a danger of theinput capacitor C1 not having enough time to charge in during theoff-time of the half-cycle.

By monitoring the input of the power supply 124, the control circuit 114of the dimmer 100 of the present invention is able to determine when theinput voltage has dropped to a level that is inappropriate for continuedcharging of the input capacitor C1. For example, if the sense voltageV_(S) falls below a first voltage threshold V₁, then the capacitor C1needs a greater time to properly charge and the on-time is decreased. Onthe other had, if the sense voltage V_(S) remains above the firstvoltage threshold V₁, the input capacitor C1 is able to properly chargeeach half-cycle.

FIG. 3 shows a flowchart of the process for monitoring the sense voltageV_(S) and determining whether to change the on-time t_(ON) in responseto the value of the sense voltage V_(S). The process of FIG. 3 runs eachhalf-cycle of the AC voltage. The on-time t_(ON) is changed in responseto the maximum on-time t_(ON-MAX) being decreased or increased if themaximum on-time is less than a desired on-time, t_(ON-DESIRED), of thedimmer. The desired on-time t_(ON-DESIRED) is determined by the controlcircuit 114 from the inputs provided by the buttons 118. The maximumon-time t_(ON-MAX) is only changed if the sense voltage V_(S) is belowthe first voltage threshold V₁ or if the sense voltage V_(S) is abovethe second voltage threshold V₂ and the maximum on-time t_(ON-MAX) hasnot returned to the maximum on-time limit, t_(ON-MAX-LIMIT), of thedimmer 100.

The flowchart of FIG. 3 begins at step 310 at the beginning of eachhalf-cycle. First, at step 312, the sense voltage V_(S) is sampled onceimmediately after the FETs are turned off. If the sampled sense voltageV_(S) is less than the first voltage threshold V₁ at step 314 and themaximum on-time t_(ON-MAX) is greater than the present on-time t_(ON) atstep 316, the dimmer has detected that the sense voltage has droppedbelow the first voltage threshold V₁. Then, the maximum on-timet_(ON-MAX) is set to the present on-time t_(ON) at step 318 and themaximum on-time t_(ON-MAX) is decreased by a first predetermined timeincrement t₁ at step 320. The first predetermined time increment t₁preferably corresponds to 1% of the dimming range. If the maximumon-time t_(ON-MAX) is less than the present on-time t_(ON) at step 318,the maximum on-time t_(ON-MAX) is decreased by a first predeterminedtime increment t₁ at step 320.

At step 322, a determination is made as to whether the maximum on-timet_(ON-MAX) is less than the desired on-time t_(ON-DESIRED). If so, theon-time t_(ON) is set to the present value of the maximum on-timet_(ON-MAX) at step 324. Since the sense voltage is only sampled afterthe FETs are turned off (at step 312), the change to the on-time t_(ON)at step 320 will affect the on-time of the dimmed hot voltage during thenext half-cycle. The process then exits at step 326 for the currenthalf-cycle to begin again at the beginning of the next half-cycle. Ifthe maximum on-time t_(ON-MAX) is greater than the desired on-timet_(ON-DESIRED) at step 322, then the dimmer has returned to normaloperating conditions. The desired on-time t_(ON-DESIRED) is used as theon-time at step 328 and the process exits at step 326.

If the sense voltage V_(S) is greater than the first voltage thresholdV₁ at step 314 and the sense voltage is less than the second voltagethreshold V₂ at step 330, then the maximum on-time t_(ON-MAX) and thusthe on-time t_(ON) are not changed. If the sense voltage V_(S) isgreater than the second voltage threshold V₂ at step 330, the processmoves to step 332 where a determination is made as to whether thepresent maximum on-time t_(ON-MAX) is less than the maximum on-timelimit t_(ON-MAX-LIMIT). If not, the maximum on-time t_(ON-MAX) hasreturned to the limit and the maximum on-time t_(ON-MAX) and the on-timet_(ON) are not changed. However, if the present maximum on-timet_(ON-MAX) is greater than the maximum on-time limit t_(ON-MAX-LIMIT) atstep 332, then the maximum on-time t_(ON-MAX) is increased by a secondpredetermined time increment t₂ for the next half-cycle at step 334. Thesecond predetermined time increment t₂ preferably corresponds to 0.5% ofthe dimming range.

FIG. 4 shows the voltage waveforms of the dimmer 100 operating with inaccordance with the present invention as the voltage at the input of thepower supply 124 is falling. The upper waveform shows the dimmed hotvoltage, which is across the ELV load 104. In the first few line cycles(a), (b), (c), and (d), the dimmed hot voltage is zero for only a smalloff-time at the end of each half-cycle. The lower waveform shows thesense voltage V_(S), which is a scaled version of the voltage at theinput of the power supply 124. During the off-time each half-cycle, theinput capacitor C1 of the power supply 124 charges and the sense voltagerises. During the first few cycles (a), (b), (c), the sense voltageremains above the first voltage threshold V₁.

During the fourth half-cycle (d), the sense voltage falls below thefirst voltage threshold V₁. The control circuit 114 decreases theon-time of the dimmed hot voltage during the next half-cycle (e) by thefirst time increment t₁. Thus, the input capacitor C1 has more time tocharge during the off-time of the next half-cycle (e).

However, during the half-cycle (e), the sense voltage once again fallsbelow the first voltage threshold V₁. So, the control circuit 114decreases the on-time of the dimmed hot voltage during the nexthalf-cycle (f) by the first time increment t₁. The cycle repeats againuntil the sense voltage does not fall below the first voltage thresholdV₁ during the half-cycle (g). Now, the on-time of the dimmed hotwaveform is held constant through the next half-cycles (h), (i).

FIG. 5 shows the voltage waveforms of the dimmer 100 after a low-voltagecondition has been detected and the sense voltage V_(S) is rising. Theon-time of the first few half-cycles (j), (k), (l), (m), (n) of thedimmed hot waveform (the upper waveform of FIG. 5) is the decreasedon-time (that was determined from the description of FIG. 4). Now, thevoltage at the input of the power supply 124, and thus the sense voltageV_(S), is rising (as shown in the lower waveform of FIG. 5).

During half-cycle (n), the sense voltage remains above the secondvoltage threshold V₂. Therefore, the control circuit 114 increases themaximum on-time of the dimmed hot waveform during the next half-cycle(o) by the second time increment t₂. While the sense voltage continuesto remain above the second voltage threshold V₂, the control circuit 114continues increasing the maximum on-time each half-cycle by the secondtime interval t₂ until the maximum on-time is equal to the originalmaximum on-time.

The dimmer 100 of the present invention has been described such that thecontrol circuit 114 is operable to change the maximum on-time t_(ON-MAX)from one half-cycle to the next. However, it may be preferable to onlychange the maximum on-time t_(ON-MAX) from one line-cycle to the next.Many dimmers are operable to drive multiple types of lighting loads.Some lighting loads, such as magnetic low-voltage (MLV) lighting loads,are susceptible to asymmetries that produce a DC component in thevoltage across the load. For example, the magnetic low-voltagetransformers required for MLV lighting may saturate and overheat whenthe load voltage has a DC component. When the on-time is changed fromone half-cycle to the next, the voltage across the lighting load with beasymmetric and a DC component will be present in the voltage. On theother hand, when the on-time is only changed from one line-cycle to thenext, the load voltage will remain symmetric and the problem ofsaturating or overheating the MLV transformer will be avoided.

While the dimmer 100 of the present invention was described primarily inregards to control of ELV loads, the dimmer may be used to control otherload types, for example, incandescent or MLV loads.

Although the present invention has been described in relation toparticular embodiments thereof, many other variations and modificationsand other uses will become apparent to those skilled in the art. It ispreferred, therefore, that the present invention be limited not by thespecific disclosure herein, but only by the appended claims.

1. A two-wire dimmer for control of a lighting load from a source of ACvoltage, comprising: a semiconductor switch operable to be connectedbetween said lighting load and said source of AC voltage; saidsemiconductor switch having a conducting state and a non-conductingstate; a power supply operable to draw current from said source of ACvoltage when said semiconductor switch is in said non-conducting state;and a control circuit operable to control said semiconductor switch intosaid conducting state for an on-time each half-cycle of said AC voltage;said control circuit coupled to an input of said power supply formonitoring a voltage of said power supply; wherein said control circuitis operable to decrease said on-time when said input voltage of saidpower supply falls below a first predetermined voltage threshold.
 2. Thetwo-wire dimmer of claim 1, wherein said power supply has an input forreceipt of an input voltage and said control circuit is coupled to saidinput of said power supply for monitoring said input voltage of saidpower supply.
 3. The two-wire dimmer of claim 2, wherein said controlcircuit is operable to decrease said on-time by a first predeterminedtime interval.
 4. The two-wire dimmer of claim 3, wherein said controlcircuit is operable to increase said on-time when said input voltage ofsaid power supply remains above a second predetermined voltagethreshold.
 5. The two-wire dimmer of claim 4, wherein said controlcircuit is operable to increase said on-time by a second predeterminedtime interval.
 6. The two-wire dimmer of claim 5, further comprising aresistive voltage divider for providing a scaled-down representation ofsaid input voltage of said power supply to said control circuit.
 7. Amethod for controlling the intensity of a lighting load from a source ofAC voltage in a dimmer comprising a semiconductor switch coupled betweensaid lighting load and said source, a control circuit for controllingsaid semiconductor switch, and a power supply for powering said controlcircuit; of ensuring that a power supply for powering low-voltagecircuitry of a dimmer is able to properly charge, the dimmer adapted tobe coupled between a source of AC voltage and a lighting load, saidmethod comprising the steps of: scaling down a voltage of said powersupply to produceproducing a sense voltage in response to a voltage ofsaid power supply; measuring said sense voltage; comparing the saidsense voltage to a first predetermined voltage threshold; and changing aconduction time of said semiconductor switch dimmer based on the resultof the step of comparing, such that said power supply has enough time tocharge.
 8. The method of claim 7 11, wherein said voltage of said powersupply comprises an input voltage of said power supply.
 9. The method ofclaim 8 11, wherein changing said conduction time comprises decreasingsaid conduction time by a first predetermined time when said sensevoltage falls below said first predetermined voltage threshold.
 10. Themethod of claim 9, further comprising the steps of: comparing said sensevoltage to a second predetermined voltage threshold; increasing saidconduction time by a second predetermined time when said sense voltagerises above said second predetermined voltage threshold.
 11. The methodof claim 7, wherein the step of producing a sense voltage in response toa voltage of said power supply further comprises scaling down saidvoltage of said power supply to produce said sense voltage.